Informations
The SiNANO Institute is pleased to co-organize a dedicated workshop with the FAMES Pilot Line during ESSERC 2026.
The SiNANO Workshops started within the framework of the ESSDERC-ESSCIRC Conferences in 2005, addressing various topics in Nanoelectronics. Over the past 19 editions, these Workshops have been highly successful and well-attended. This year, we propose a joint Workshop FAMES Pilot Line – SiNANO Institute as several FAMES partners are SiNANO Institute’s members.
The workshop will bring together leading researchers from across Europe to discuss some of the key technologies driving the next generation of semiconductor devices and systems. Topics will include FD-SOI, embedded non-volatile memories, RF technologies, 3D sequential integration, advanced packaging, power management, and the role of these technologies in enabling low-power and AI-driven applications.
The workshop will open with an overview of the FAMES Pilot Line and the SiNANO Institute, before a series of technical presentations delivered by experts from CEA-Leti, Tyndall National Institute, and other leading research organisations.
Joint Workshop FAMES Pilot Line – SiNANO Institute: FDSOI Pilot Line Insights and Perspective
This Workshop will be the first to present in-depth technical results obtained through the FAMES Pilot Line project on the development of FD-SOI at 10nm and 7nm nodes, combined with non-volatile memories (NVM) and 3D options, RF components and smart PMIC (Power Management Integrated Circuit), providing a pathway to deliver high-performance, low-power consumption solutions for future chips.
This FAMES Pilot Line started in Dec. 2023 with the aim of providing chipmakers, startups, fabless companies, and academics with access to cutting-edge FD-SOI technologies, embedded non-volatile memories, 3D integration, RF components, and power management solutions.
Programme
FAMES and SiNANO Introductions
14:00 – 14:15
Dominique Noguet, CEA-Leti FAMES Coordinator
Abstract “The FAMES pilot line, opportunities for next generation of chips”: FAMES is one of the five Pilot Lines launched by the Chips JU as part of the Chips Act 1 to support European sovereignty in the area of micro and nano electronics. Five technologies are being developed in the framework of this ambitious 830M€ initiative: FD-SOI, eNVM, RF passive components, 3D integration and power management IC, along with an eco-innovation program. This interlocutory talk will give an overview of the activities of FAMES and will stress how the semiconductor ecosystem can gain access to the technologies and the Pilot Line of the project.
Biography: Dominique Noguet is the coordinator of the FAMES Pilot Line, and VP at CEA-Leti. Prior to this role he held several positions as digital IC designer, lab manager and department manager. He led many projects at a national level and in European frameworks (FP5, FP6, FP7), and large industrial partnerships. Dominique has authored or co-authored 100+ scientific papers (several best paper awards), several book chapters and 15 patents. He was a reviewer and a member of scientific committees of international conferences and a member of journal editorial boards. He was conference chair and TPC chair of several international conferences, and is an IEEE Senior Member. Dominique holds an engineering degree of the National Institute of Applied Sciences (INSA) in electrical engineering in 1992, and a PhD from National Polytechnical Institute of Grenoble (INPG) in 1998.
Giorgos Fagas, SiNANO Institute’s Director
Abstract: The SINANO Institute is a leading European academic and scientific association dedicated to advancing nanoelectronics research and innovation. It brings together top universities, research centres, and industry partners to foster collaboration, knowledge exchange, and strategic alignment across Europe. SINANO plays a key role in shaping research agendas, supporting emerging technologies, and strengthening Europe’s position in the global semiconductor landscape. Through coordinated initiatives, expert working groups, and engagement with policy frameworks, SiNANO promotes excellence in science and education. Its activities contribute to the development of next-generation electronic systems, enabling technological progress in areas such as advanced computing, sensing, and energy-efficient devices.
Biography: Pr Giorgos Fagas (PhD, MBA) is Director of Strategic Development at Tyndall National Institute and a member of its Executive Leadership Team, where he shapes the institute’s international strategy and leads major cross-cutting initiatives. An expert in advanced semiconductors, nanoelectronics and quantum technologies, he has played a central role in European research and innovation, contributing to Ireland’s Silicon Island strategy and the EU Chips Act through the implementation of pilot lines such as FAMES, horizon scanning and coordinating numerous EU-funded projects. Advancing international collaboration, expanding pilot line activities, and driving technology foresight efforts that strengthen Europe’s semiconductor ecosystem and global partnerships, Giorgos is the Director of SiNANO and coordinator of the ICOS2 EU Coordination and Support Action on ‘International Cooperation on Semiconductor Innovation and Supply Resilience’.
Next generations of FD-SOI technology for low-power and RF applications
14:15 – 14:40
Thierry Poiroux – CEA-Leti
Abstract: In this presentation, we will first detail the 10 nm FD-SOI technology developed in the FAMES pilot line, emphasizing performance boosters to meet specifications. The second part will discuss FD-SOI transistor specificities and their exploitation at the circuit level. We will explore how these unique characteristics can be leveraged to enhance circuit performance and efficiency. The presentation aims to provide insights into the technological advancements and practical applications of FD-SOI technology.
Thierry Poiroux received the M.S. degree from Ecole Centrale Paris, France, in 1995 and the Ph.D. degree from the University of Nantes, France, in 2000. After a Ph.D. work carried out at the Commissariat à l’Énergie Atomique/Laboratoire d’Electronique et de Technologie de l’Information (CEA–Leti), Grenoble, France, and Matra MHS on plasma process-induced damage, he joined CEA–Leti as a Research Staff Member in 2000. Until 2002, he was involved in partially and fully depleted silicon-on-insulator (SOI) process integration and compact modeling. From 2002 to 2010, he worked on advanced device architectures and was in charge of multiple-gate device modeling, planar double gate process integration and fabrication of graphene-based transistors. In 2011 and 2012, he has been the Head of the Innovative Device Laboratory of CEA–Leti, dedicated to the development of advanced CMOS technologies. From 2012 to 2018, he developed the second version of the L–UTSOI compact model, selected by the Si2 Compact Model Coalition as a standard industrial model for fully-depleted SOI technologies. From 2018 to 2021, he was the head of the Simulation and Compact Model Laboratory of CEA–Leti. From 2021 to March 2025, he was in charge of the Characterization, Design and Simulation Department, and he is currently project leader. He has authored or coauthored five book chapters and about 190 papers and communications, and he is author or co-author of about 20 patents.
Valeriya Kilchytska - UCLouvain
Abstract: In this presentation, we will first detail the 10 nm FD-SOI technology developed in the FAMES pilot line, emphasizing performance boosters to meet specifications. The second part will discuss FD-SOI transistor specificities and their exploitation at the circuit level. We will explore how these unique characteristics can be leveraged to enhance circuit performance and efficiency. The presentation aims to provide insights into the technological advancements and practical applications of FD-SOI technology.
Valeriya Kilchytska is Senior Researcher, Logistic Director assuring scientific lead of the WELCOME Electrical Characterization Platform at UCLouvain. She received her PhD degree in semiconductor and dielectric physics from Taras Shevchenko National University of Kyiv, Ukraine in 1997. Her PhD work is on the electrical and radiation properties of Silicon-on-Insulator (SOI) structures. Then she worked at Kyiv Institute of Semiconductor Physics on the bias-temperature processes in SOI. In 2001, she was a visiting researcher at the Chalmers University of Technology, Sweden, for characterization of SiC MOS structures. She joined UCLouvain in 2002. She has a long-term experience in characterization, simulation and modelling of advanced devices with a focus on wide frequency band and noise characterization, performance assessment as well as cryogenic, high-temperature and radiation behavior. She has authored or co-authored > 300 scientific papers and conference contributions. She is a reviewer for numerous scientific journals and a TPC member of several conferences. Since 2023, she is a Deputy Director of SINANO Institute.
What achievements FAMES already produced for the development of Embedded Non Volatile Memories in Europe
14:40 – 15:05
Gabriel Pares – CEA-Leti
Abstract: Emerging eNVM are essential add-on technologies for FD-SOI platforms at the 10 and 7 nm nodes where flash will no longer be working. In FAMES pilot line we are developing four main flavors of eNVM (OxRAM, FeRAM, MRAM and BEOL Fe(M)FET), each of which having significant advantages for addressing specific applications targeted for FD-SOI, particularly for artificial intelligence and security. This presentation will give an overview of the status we have reached and the progresses made at the midterm of FAMES timeline.
Gabriel Parès has an Engineer degree in “material science” from l’Institut National des Sciences Appliquées (INSA) de Lyon, France and a postgraduate degree in “semiconductor material sciences” from the University of Lyon. He has been working for 33 years in semiconductors and MEMS industry in industrial and R&D fields, formerly for STMicroelectronics and MEMScap, then he joined CEA-leti in 2004. He has been working from 2010 to 2020 in the field of 3D integration and advanced packaging technologies. Since 2021 he is project manager in the Laboratory of Memories and Computing in charge of the work package dedicated to embedded Non Volatile memories of the FAMES pilot line. He holds 18 patents and he is the author of 19 publications in different fields of semiconductors technologies.
TBD
15:05 – 15:30
Piotr Wisniewski - CEZAMAT
Piotr Wiśniewski, Ph.D. Eng., is a Head of Intelligent Semiconductor Systems Division (SEMINSYS), Centre for Advanced Materials and Technologies CEZAMAT, Warsaw University of Technology. He received his MSc. Eng. degree in microelectronics, photonics, and nanotechnology, and a Ph.D. degree in electrical engineering from Warsaw University of Technology (WUT). Currently is the Head of the Intelligent Semiconductor Systems Department (SEMINSYS) and an assistant professor at the Centre for Advanced Materials and Technologies CEZAMAT WUT, responsible for managing the semiconductor technology line and R&D activities of the department. His research interests and expertise cover physics, modeling, and technology of semiconductor devices for micro / nano-electronics and photonics. He has been actively involved in national and international projects as a principal investigator or researcher, supported by various research agencies
Solidly Mounted Lithium Niobate Bulk Acoustic Wave Filters for the FR3 range
15:50 – 16:15
Alexandre Reinhardt – CEA-Leti
Abstract : Crowding of the sub-6 GHz wireless spectrum and the need for increasing data rates have pushed 5G to exploit mmWave frequencies. However, this limits data transfer to short distance and line-of-sight links. In view of this, 6G proposes to exploit the FR3 range (7-24 GHz), which seems a promising compromise. Mobile communication will however have to share the spectrum with already existing satellite or emergency services. This requires suitable bandpass filters. In this talk, we present on-going work at CEA Leti towards bringing acoustic filters from the sub-6 GHz to the FR3 range by leveraging the use of single crystal piezoelectric materials.
Alexandre Reinhardt is a senior technical expert with 25 years of experience in developing acoustic wave resonators and filters for the wireless communication industry. After a PhD at the FEMTO-ST Institute (Besançon, France) sponsored by Temex (now Qualcomm France), he joined CEA-Leti in 2006. His research focuses particularly on bulk acoustic wave resonators, their modeling and the design of these devices, to answer the need to continuously increase operation frequencies and quality factors. In the past decade, he has particularly investigated the use of single crystal highly piezoelectric materials such as lithium niobate, which now find applications in the filtering industry.
Advancing 3D Sequential Integration: Process Innovations and Future Applications
16:15 – 16:40
Daphnée Bosch – CEA-Leti
Abstract: 3D Sequential Integration (3DSI) enables the stacking of diverse device layers with unparalleled contact density thanks to lithographic alignment. The FAMES project aims to expand the applicability of 3DSI to “More than Moore” applications, targeting advanced imaging systems, energy-efficient computing, and RF circuits. This presentation will provide key process elements for realizing components in 3D sequential integration and offer a vision of the targeted applications for the future. We summarize our latest advancements, including the development of versatile 2.5V n & p SOI MOSFETs fabricated entirely at 400°C, overcoming critical low-temperature challenges and enabling large-scale industrial adoption. Additionally, we demonstrate the first radio-frequency circuits fabricated in the top-tier of a full 3D Sequential Integration process at mmW for 5G applications, showcasing the feasibility of vertical co-integration without degradation despite the close vicinity of both tiers.
Daphnée Bosch received the M.Sc. degree in micro and nanotechnologies for integrated systems from Grenoble-INP Phelma, Politechnico di Torino and EPFL in 2017 and the Ph.D. degree in microelectronics from the University of Grenoble-Alpes in 2020. Her current research interest is advanced CMOS technologies, focusing on 3D sequential integration and fully depleted SOI devices. She has authored over 25 papers in international conferences or journals in this field and has been part of the IEDM process technology committee. Currently, she is in charge of 400°C low temperature devices development in the FAMES project.
The Rise of Heterogeneous Integration and 3D architectures as key enablers in the AI era.
16:40 – 17:05
Emmanuel Ollier – CEA-Leti
Abstract: The push toward sub-2nm transistor nodes and innovative device architectures is essential to meet the performance demands in the AI era. Yet, this alone is no longer sufficient. The soaring computational needs of cloud servers and edge-AI call for groundbreaking architectures that drastically cut data movement, latency, and power consumption. These new architectures are made possible by major advances in advanced packaging and heterogeneous integration, technologies that have become pivotal in semiconductor ecosystems. This presentation will demonstrate how the FAMES Pilot Line drives innovation in advanced packaging, notably through small-pitch hybrid bonding and through-silicon via (TSV) technologies. It will also showcase how these technologies enable novel architecture designs for computing and RF systems.
Dr. Emmanuel Ollier is the EU Program Manager at CEA-Leti’s Semiconductor Components Division. Previously, he led the Laboratory of 3D Integration and Advanced Packaging Technologies at CEA-Leti. With 17 years of experience in the semiconductor industry (including roles at Thales, Atmel, NXP, EM Microelectronics) he holds 22 patents and has authored 45 papers and international conference presentations. Dr. Ollier earned a PhD in Material Sciences and an Engineering Degree from the French National School of Physics and Chemistry of Bordeaux. His expertise focuses on the heterogeneous integration of semiconductor and photonic technologies, with applications spanning High-Performance Computing, Edge-AI, RF communications, smart sensors and displays, and power electronics.
Small inductors for DC-DC converters: Power Management Integrated Circuits.
17:05 – 17:30
Sambuddha Khan – Tyndall National Institute
Abstract: High-frequency on-chip power supplies demand inductors co-located with power management ICs, yet monolithic BEOL integration of magnetics is constrained by thermal budget and thin metallisation. This talk presents Tyndall’s magnetics-on-silicon platform and the heterogeneous integration solution developed within the FAMES Pilot Line: model-based design of stripline micro-inductors (5–10 nH, 20–50 MHz) for multi-level buck converters, optimised CoZrTa/AlN laminated cores, and wafer-level fabrication with quality factors above 8. A tether-free micro-transfer-printing process integrates large-footprint inductor chiplets onto glass substrates and into silicon trenches, preserving inductance within ±10%. Prospects for buried inductor–capacitor power networks in interposers and FAMES access will be discussed.
Dr Sambuddha Khan is a Senior Scientist and Technical Lead at Tyndall National Institute, Ireland, where his research focuses on the design, fabrication, and heterogeneous integration of MEMS and micro-components, including integrated magnetics, piezoelectric transformers, and AlScN-based RF acoustic resonators for power-supply-on-chip applications. He serves as Programme Manager for Tyndall’s participation in the Chips JU FAMES Pilot Line project and has led research programmes funded by Horizon Europe, Research Ireland, and Enterprise Ireland. Before joining Tyndall, he was a postdoctoral researcher at the University of California, Irvine, working on a DARPA-funded programme on inertial-grade silicon MEMS gyroscopes. Dr Khan received his PhD from the Indian Institute of Science, Bengaluru, in 2014, and lectures at University College Cork on MEMS and microfabrication.
Venue
www.auditoriumpalma.com
