Abstract
We are please to announce that the 2026 IRDS/ISRDS Workshop will take place this year in Granada.
During two days, experts will present the latest update of main IRDS chapters, and discuss new direction in computing, and new directions of materials & devices for computing.
Day 1 – IRDS – Annual Update of Roadmap Summaries
Day 2 – 2D Tutorial & ISRDS (International Symposium on Roadmapping Devices and Systems)
IRDS represents the main International Roadmap of the Electronic Industry. The main challenges and possible solutions covering materials, devices and systems for many applications in the next 15 years will be highlighted.
The ISRDS will be dedicated to new direction in computing, including neuromorphic, probabilistic, reversible, and quantum computing, and new directions of materials & devices for computing, including 2D and ferroelectric materials, steep slope devices, quantum materials and devices, spintronics and cryogenic electronics.
Venue
Assembly Hall of the Faculty of Medicine
Tower B, Floor 1
University of Granada
PTS Parque Tecnológico de la Salud
Avda. Doctor Jesús Candel Fábregas 11, 18016 Granada
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EUROSOI-ULIS 2026
20-22 May, 2026
The IRDS/ISRDS Workshop is organised as part of the EUROSOI-ULIS Conference, which will be held at the same venue, on May 20-22, 2026.
Important Dates
Notification of acceptance: March 31, 2026
Registration opening: March 1, 2026
Early Bird registration deadline: April 20, 2026
Dates of the congres: March 20-22, 2026
Preliminary Programme
Day 1 | IRDS – Annual Update of Roadmap Summaries | 18 May, 2026
Regional Greetings (US, EU, Japan)
United States: Paolo Gargini, US IRDS Chair
European Union : Francis Balestra, SiNANO Institute
Japan: Yoshihiro Hayashi, SDRJ Chair/Keio University
Yield Enhancement (YE) - Slava Libman
Abstract: This presentation focuses on recent developments in Yield Enhancement, one of the most critical areas enabling advanced semiconductor manufacturing. The Yield Enhancement forum and its associated initiatives incorporate contributions from team members across the United States, Europe, and Japan. The scope of Yield Enhancement prioritizes contamination control challenges, for which solutions often require many years to develop and mature. Over the past year, much of the work has focused on advancing the understanding of defectivity in next-generation devices, informed by extensive collaboration between the Yield Enhancement and
Biography: Dr. Slava Libman is Chief Executive Officer of FTD Solutions, a company advancing digital platforms for water management and environmental performance in industrial operations. He brings three decades of experience in water technology, with deep expertise in the semiconductor sector across technical, operational, and executive leadership roles. Dr. Libman serves as Co-Chair of the semiconductor technology roadmap, where he leads initiatives in Environmental Sustainability and Yield Enhancement. He is also involved in the development of industry standards in these domains and organizes technical conferences and webinars that shape cross- industry collaboration. Prior to co-founding FTD Solutions, Dr. Libman held senior roles at a leading semiconductor manufacturer, a global architecture and engineering firm, and a premier analytical laboratory. He earned a Ph.D. in Environmental Engineering from the Technion – Israel Institute of Technology.More Moore teams.
Applications, Systems, & Architectures (ASA) - Vladimir Getov
Biography: Vladimir Getov is a professor of distributed and high‑performance computing at the University of Westminster and an active IEEE Computer Society volunteer since the mid‑1990s. He has served on the IEEE CS Board of Governors and contributed to both the Publications Board and the Technical and Conference Activities Board. He has held numerous leadership roles, including area editor for Computer since 2008 and chair positions for several IEEE conferences. His career spans industry and academia, with early work in computer development and later academic appointments in Southampton and Westminster. He has played a key role in international initiatives such as the PARKBENCH Committee, the Java Grande Forum, and the Open Grid Forum. Getov has received multiple prestigious awards and is a Senior Member of IEEE and ACM as well as a BCS Fellow.
Abstract: Since the IRDS inception in 2017, the Applications Benchmarking (AB) and Systems and Architectures (SA) International Focus Teams (IFT) have contributed the tops down guidance to the IRDS communities. AB shared insight into what we need to compute and tracked the capabilities of systems to achieve those needs while SA provided insight on where that computing occurs across system categories from IoT Edge beacons to exascale supercomputers. The rapid adoption of generative AI has provided an unprecedented stochastic shock to the entire IT ecosystem, which demands changes to our methodology and has led to the merger of the two teams.
Coffee Break
Autonomous Machine Computing (AMC) - Jean-Luc Gaudiot, UCI
Abstract: Robotic workloads are fundamentally characterized by continuous sensor streams, sparse and irregular computation, tight perception–action loops, and strict real-time and energy constraints. This AMC roadmap update focuses on the core message that dataflow architectures are uniquely well suited to these demands, as they enable event-driven execution, fine-grained parallelism, and locality-aware computation across heterogeneous sensing, learning, and control pipelines. By aligning computation with data availability rather than instruction sequencing, dataflow architectures offer superior scalability, energy efficiency, and responsiveness, making them a critical enabler for autonomous machines operating in dynamic, real-world environments under the IEEE IRDS framework.
Biography: Jean‑Luc Gaudiot is a Distinguished Professor of Electrical Engineering and Computer Science at the University of California, Irvine. He previously served as Professor at the University of Southern California and later chaired the EECS Department at UCI, where he led significant growth and faculty recruitment. He is the recipient of the 2026 Richard E. Merwin Award for Distinguished Service. He has held major leadership roles within the IEEE and the IEEE Computer Society, including serving as President of the IEEE Computer Society in 2017. His research focuses on parallel system programmability, hardware‑based computer security, and autonomous driving systems, with nearly 300 refereed publications. He was elected IEEE Fellow in 1999 and AAAS Fellow in 2007.
Factory Integration (FI) - Supika Mashiro, TEL
Abstract: Factory Integration includes everything that is needed to keep semiconductor manufacturing operation in the Fab undisrupted at affordable cost and in sustainable manner. Its planned focus areas in coming version, such as Digital Twin interoperability in fab and beyond, smart manufacturing advancement through adoption of robotics, and security aspects of semiconductor manufacturing operations, will be discussed in this presentation.
Biography: Supika Mashiro works as an Advisor for Tokyo Electron Limited at its HQ in Tokyo, Japan. She has been involved in Factory Integration (FI) IFT of IRDS since its inauguration in 2016 and a cochair since 2017. Her area of interest and involvement encompasses smart manufacturing as well as environment and safty/ Sustainability road-mapping and related industry standard development. Contact her at supika.mashiro@tel.com.
Metrology (MET) - Carlos Beitia, CEA
Abstract: Today industry trend is application driven by system architecture solutions. This was one of the transformative reasons from the old ITRS process-device-technology centered roadmap toward IRDS System and Device centered. This transformation of the industry cannot be done without yield and high-volume manufacturing solution. Metrology need to embrace the new paradigm and transform itself from a material and process centered control tool to at most holistic innovation and acceleration one. Consequently, from the holistic approach, metrology will need to consider Material to System Technology Co Optimization MSCO needs and cross domain data and knowledge exchange to support this approach. In the methodology and tools aspects metrology need to integrate IA to break knowledge and data silos in the FAB to accelerate yield learning. Finally at the material and process level metrology will need to track traditional issues from Material/Process perspective but will need to include System/application metrology data that can add constraints or degree of freedom for the MSCO approach.
Biography: More than 25 years in semiconductor from Research, R&D up to Industrial application. September 2022-now, Key Account Manager CEA-Leti, Materials Program Line Manager and Metrology Expert for the Technological Research Division. 2020-2022 Vice President Strategic Alliance at Unity-Semiconductor, 2029 Vice President R&D Unity Semiconductor. From 2009-2019 at Leti, work at different positions in metrology activities (Metrology R&D business development, Metrology Silicon Platform Division Deputy Manager, Scientific Manager of In-line Metrology Laboratory). Previously Application Engineer for 8 years with KLA-Tencor from junior to senior worldwide support.
Lithography and Patterning - Mark Neisser
Abstract: The IRDS 2025 lithography and Patterning roadmap has recently been published. High NA exposure tools are in full use in chip process development and are expected to be used in production as early as next year. They provide better resolution and simpler processes for upcoming logic products but also have a smaller field size. Key challenges are stochastics, process control, overlay, small field sizes and cost. Addressing these challenges will require improved masks, higher power light sources, improved resists and many process improvements. The requirements for better interchip connections are expected to drive improved packaging lithography. After 0.55NA lithography, hyper NA EUV with an NA in the range of 0.75 may be implemented if it is cost effective as a replacement for 0.55NA EUV with multiple patterning. Research efforts on shorter wavelengths than EUV are underway, but so far there is no consensus or feasibility demonstration on any of the several wavelengths under consideration. Nor are there device structures in the current IRDS roadmaps that clearly need the capabilities of a shorter wavelength. Device structures are becoming more three dimensional, with some circuit elements moving to the back of the chip. This creates challenges in overlay and patterning, but slows down the rate of scaling on the front of the chip.
Biography: Mark Neisser is a chair professor in the School of Integrated Circuits at Tsinghua University. He is also the Director of the Photoresist lab at the Integrated Circuit Research Platform at the International Innovation Center of Tsinghua University, Shanghai. He received his B.S. degree in chemistry from Cornell University and his M.S. and Ph.D. degrees in chemistry from the University of Michigan. He is the author of more than 30 US patents, over 100 journal papers and has co-authored two book chapters. He is the chairman of the IRDS roadmap committee for lithography and patterning. Dr. Neisser worked at IBM doing semiconductor lithography research, followed by positions managing research and development of photoresists and of ancillary materials for lithography. His current research interests involve EUV resists, semiconductor patterning and related materials, and the physics of imaging or patterning such materials.
Lunch
More than Moore (MtM) - Alan O’Riordan, Tyndall
Prof Alan O’Riordan is Head of the Precision Electrochemical Nanosensor Research Group, comprising support and research staff, postdoctoral researchers, and PhD students. The Group is developing nanoelectrochemical sensor technologies on silicon chip substrates, providing highly sensitive, selective, and reliable measurements. Their work is focused on smart sensors and systems for sustainable agri-food and environmental applications. He is a Principal Investigator in the Research Ireland Research Centre Vistamilk and leads the IEEE International Focus Team on More-than-Moore, part of the IEEE International Roadmap for Devices and Systems.
More Moore (MM) - Mustafa Badaroglu, Qualcomm
Abstract: Distributed AI is revolutionizing human productivity, bridging the gap between digital agents and physical AI systems. To meet the demands of this era, the future of AI relies on advanced ‘More Moore’ technologies, such as GAA, CFET, 3D devices, next-generation memory, and high-performance fabrics to enable massive scalability. In this talk, we will present the IRDS More Moore roadmap for the next 15 years, offering a solution path to integrate these technologies and drastically boost AI efficiency metrics (TOPS/W and TOPS/mm²).
Biography: Mustafa Badaroglu is Director of Engineering at Qualcomm for AI chipset/system development with focus on system-technology-co-optimization (STCO), custom memory for data center, mobile, compute, and XR products. Across more than 30 years of industry experience he had various assignments for the design and management of mobile, compute, graphics, and automotive chipsets from concept to volume production, deployment of AI platforms for automotive and smart manufacturing, process technology selection/ramping, analog and digital design automation, and STCO/DTCO. He holds more than one hundred published patents, and (co)-authored over one hundred publications in scientific journals/proceedings. He is a workstream member of American Semiconductor Innovation Coalition (ASIC), Si2 alliance, DRAM JEDEC, and IEEE IRDS More Moore global chair.
Packaging Integration (PI) - Dev Gupta, APSTL
Dr. Dev Gupta is both a Metallurgist and a Mathematician and has combined both since the 1980s to quickly develop robust and scalable technologies & processes that have transformed industries ranging from Aerospace materials to Semiconductors. He has worked in Semiconductors for the last 37 yrs ( at Motorola / IBM, Intel and his own Co. APSTL of Scottsdale, AZ ) and pioneered 2/3 rds of current versions of all Adv. Packaging techs used for AI, using very high level Math. Modeling has developed in the early 1990s the Custom Process & M/C Vision driven Robotic Assembly tools that have since become industry standards and have made the mass production of Chips using AP possible, developed & designed pioneer high yielding Fabs for Substrates and done Turnkey Engr. of Fabs for many of those AP techs in both the US and Japan. He has chaired seminal IEEE Conferences and taught courses that have disseminated his inventions on Off Chip Integration at the Package level as a savior for traditional Moore’s Law.
REFERENCES
1. IEEE Electron Devices Newsletter : EDS_Oct2025-web_3.pdf
2. Mar 2026, Semiconductor Packaging News,VIEWPOINT 2026: Dr. Dev Gupta, CTO, APSTL llc
Beyond CMOS & Emerging Materials (BC &EMI) - An Chen, IFT Leader
Abstract: This talk will present the scope, structure, and recent updates of the “Beyond CMOS (BC)” chapter in IRDS including “Emerging Materials Integration (EMI)”. The BC chapter covers emerging devices and architectures beyond conventional CMOS. As dimensional scaling approaching fundamental limits, the roadmap highlights novel beyond-CMOS computing for data-centric, AI, IoT, and exascale applications.
The chapter summarizes progress in emerging memory and logic devices, device-architecture co-design, and emerging materials integration. Opportunities, key challenges, maturity, and risk factors are assessed to guide research, tool development, funding, and investment.
Biography
An Chen is the Chair of the “Beyond-CMOS” IFT of IRDS. He received his Ph.D. degree in Electrical Engineering at Yale University. He has worked at Spansion, AMD, GLOBALFOUNDRIES, and IBM, on emerging nonvolatile memories (NVMs), beyond-CMOS research, and AI models and accelerators. At IBM, he also worked on an assignment to manage two university research programs, the Nanoelectronics Research Initiative (NRI) and the Nanoelectronic Computing Research (nCORE), jointly funded by industry members with NIST and NSF. An is a Senior Member of IEEE.
Coffe Break
Mass Data Storage (MDS) - Paolo Gargini
Abstract: Although all types of digital storage and non-volatile memory technologies face challenges for increasing information density, all the conventional technologies have paths for continued development. We anticipate continued development and use of SSDs, HDDs, magnetic tape as well as continued development and implementation of new non-volatile memories. At the same time development continues on optical storage technologies as well as synthetic DNA storage for future implementation. The committee anticipates releasing the report in May 2026.
Biography: In the 70s Dr. Gargini was a researcher at Stanford University and at Fairchild Camera and Instrument. In 1980 as manager of MPU technology at Intel transferred into manufacturing the iconic 80286 and 80386. In 1996, he became Director of Technology Strategy and responsible for worldwide consortia research until 2012. He was a member of Sematech, SRC, EUV LLC, EIDEC, ASET, IMEC and SIA Boards, and Chairman of the I300I and NRI. From 1998 to 2015, Dr. Gargini was Chairman of the ITRS sponsored by the WSC. Since 2016 he is the Chairman of the IRDS sponsored by IEEE.
Cryogenic Electronics & Quantum Information Processing (CEQIP) - Emanuele Pelucchi, Tyndall
Abstract: Cryogenic Electronics and Quantum Information Processing (CEQIP) is an International Focus Team (IFT) within the IEEE International Roadmap for Devices and Systems (IRDS). CEQIP areas of coverage include superconductor electronics, cryogenic semiconductor electronics, and quantum information processing. These are developing technology areas with currently small markets but large potential. Significant technology improvements are required to meet the expected needs of applications such as quantum computing, artificial intelligence, or large-scale digital computing. This presentation covers key applications and market drivers, technology status, active research questions, technology roadmaps, and future plans.
Biography: Head of Epitaxy and Physics of Nanostructures group. Dr Pelucchi started his PhD in April 1997, working in the field of surface science and molecular beam epitaxy (MBE). His research covered MBE of II-VI materials on III-V substrates, photoemission applied to interface physics and metal-semiconductor Schottky barriers. He moved to Lausanne (EPFL) in 2001 as a research assistant (post-doc), in the group of Professor Eli Kapon. He participated to the development of research concerning metalorganic vapour phase epitaxy (MOVPE) of site controlled III-V nanostructures, working on both V-groove quantum wires and Pyramidal QDs. In May 2006 Dr Pelucchi was awarded with a Science Foundation Ireland Principal Investigator Grant. In January 2007 moved to Tyndall National Institute. where he runs the national MOVPE facility and various quantum technology projects. Dr. Pelucchi has very broad interests, spanning from surface science and epitaxy to quantum optics. He has recently acquired a relevant role in MOVPE epitaxy, having developed world leading III-V material quality and growth process understanding, while uniquely demonstrating arrays of site-controlled quantum dots and entangled photon emitters (at cryogenic temperatures).
Outside System Connectivity (OSC) - Paolo Gargini
Abstract: The Outside System Connectivity Chapter provides a 15-year forecast of the capabilities required for communication between systems or between sensors and systems. This presentation will focus on new capabilities required in cloud centers and communication of mobile devices and IoT devices through satellites to enable global internet access. Within Cloud centers, communication between processors requires ever increasing data rates, AI centers require high data rates with tight distributions of latency, and Quantum Computing needs quantum networks to enable large distributed Quantum Computers. To enable global internet access for Mobile phone and IoT devices, large array RF low earth orbit satellites have been developed that communicate directly with these devices. There are proposals for the satellites to develop an optical network with other satellites and orbiting data centers. Finally, there are proposals to have orbiting AI processing satellites networked in polar orbit to have continuous access to solar power.
Biography: In the 70s Dr. Gargini was a researcher at Stanford University and at Fairchild Camera and Instrument. In 1980 as manager of MPU technology at Intel transferred into manufacturing the iconic 80286 and 80386. In 1996, he became Director of Technology Strategy and responsible for worldwide consortia research until 2012. He was a member of Sematech, SRC, EUV LLC, EIDEC, ASET, IMEC and SIA Boards, and Chairman of the I300I and NRI. From 1998 to 2015, Dr. Gargini was Chairman of the ITRS sponsored by the WSC. Since 2016 he is the Chairman of the IRDS sponsored by IEEE.
Environment, Safety, Health & Sustainability (ESH/S) and Environmental Sustainability of Semiconductor Fabrication (ESSF) - Leo Kenny, Planet Singular
Abstract: This presentation will briefly review the evolution and development of the Environmental, Safety, Health and Sustainability (ESH/S) Functional Team, the current status and plans for our Environmental Sustainability for Semiconductor Facilities (ESSF) Work Group. The talk will also highlight key areas of risk and concern in the ESHS space for the semiconductor and adjacent industry segments and a review of future considerations to address these challenges, including the importance of recruiting new technical members for our technology roadmap work groups.
Bioghraphy: Dr. Kenny serves as a Research Professor and Senior Fellow at the Center for High Technology Materials at the University of New Mexico.
He is currently the Chair of the EHS/Sustainability Functional Team for the IRDS (International Roadmap for Devices and Systems) for the Semiconductor Industry and past Co-Chair of the Sustainable Electronics Section for INEMI, the international roadmap for the Electronics Industry.
He is also the Principal and Founder of PLANETSINGULAR, a technical consulting and advising firm focusing on smart infrastructure, organizational development, environmental technology, materials design, green chemistry, environmental sensing, smart and technical leadership strategies for EHS and Sustainability. He has held a variety of technical, managerial and leadership roles in industry, government, academic, technical consulting and nonprofit organizations.
Leo earned a BS in Ecology & Evolutionary Biology, as well as a BS in Chemistry from The University of Arizona in Tucson. Leo holds a PhD in Physical Inorganic Chemistry from Tufts University in Boston.
Next Steps and Closing Remarks- Paolo Gargini
Biography: In the 70s Dr. Gargini was a researcher at Stanford University and at Fairchild Cameraand Instrument. In 1980 as manager of MPU technology at Intel transferred intomanufacturing the iconic 80286 and 80386. In 1996, he became Director ofTechnology Strategy and responsible for worldwide consortia research until 2012. Hewas a member of Sematech, SRC, EUV LLC, EIDEC, ASET, IMEC and SIA Boards, andChairman of the I300I and NRI. From 1998 to 2015, Dr. Gargini was Chairman of theITRS sponsored by the WSC. Since 2016 he is the Chairman of the IRDS sponsored byIEEE.
Day 2 | 2D Tutorial & ISRDS (International Symposium on Roadmapping Devices and Systems) | 19 May, 2026
Tutorial “New Materials for Electronics”
"Neuromorphic computing based on 2D materials" - Andrea Capasso (INL, Braga, Portugal)
"New memory devices based on emerging materials" - Hanwool Yeon (Gwangju Institute of Science and Technology, GIST, Korea)
Emerging materials for computation compatible with CMOS - Satarship Das (Penn State University, USA)
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2D materials for computation - Xinran Wan (Nanjing University, China
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More-than-Moore applications based on 2D materials - Francisco Gamiz (UGR, Spain & FAMES)
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Sayani Majumdar - Tampere University
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New Directions in Computing
"Spiking Manifesto" Eugene Izhikevich
Abstract: Modern AI models have increasingly larger dimensions to maximize their representational capacity, requiring GPUs to perform multiplications of huge matrices. In contrast, the brain’s spiking neural networks exhibit factorially explosive encoding capacity even when their size is small. This manifesto proposes a framework for thinking about popular AI models in terms of spiking networks and polychronization, and for interpreting spiking activity as nature’s way of implementing look-up tables. This suggests a path toward converting AI models into a novel class of architectures with much smaller size yet combinatorially large representation capacity, offering the promise of a thousandfold improvement in performance. https://arxiv.org/pdf/2512.11843
Biography: Eugene Izhikevich is the founder and CEO of SpikeCore in San Diego, the founder and Chairman of the Board of Brain Corp, and the founder and Editor‑in‑Chief of Scholarpedia, the peer‑reviewed encyclopedia.
"A Hybrid Memristor-Magnetic Tunnel Junction Ising Machine" Mohammed-akib Iftakher
New Directions in Materials and Devices for Computing
New directions in materials and devices for Computing "The Dirac-Source FET and the neverending quest for steep-slope switches": Luca Selmi - University of Modena - IUNET
Abstract: The quest for reduced switching energy in digital circuits is increasingly limited by the Boltzmann tyranny, which prescribes a minimum subthreshold swing of 60 mV/dec for thermionic emission devices. Numerous steep slope transistor concepts have been proposed in the attempt to beat this limit, none of which has yet made it to mainstream technologies. In this context, we aim to present recent results on the Dirac-Source Field Effect Transistor, a recently proposed steep slope FET exploiting the unique properties of Dirac-material / Semiconductor junctions.
Biography : Luca Selmi (PhD 1992, Fellow IEEE 2015) is Professor of Electronics at Università degli Studi di Modena e Reggio Emilia. His research interests cover modeling, simulation, and characterization of micro/nanoelectronic devices for switching and sensing. They led him to co-author more than 350 peer-reviewed publications, book chapters and a Cambridge University Press book on Nanoscale MOS Transistors. He has served as IEEE EDL associate editor, as TPC member of IEEE IEDM, VLSI Symposium, ESSDERC and as chair of numerous international conferences and events in the area of electron devices. From 2017 to 2022 he directed the IUNET consortium on nanoelectronics and he currently coordinates the EU Chips-JU project “AttoSwitch”.
"Ferroelectrically switchable quantum geometry for in-memory computing" Peng Song - NTU
Abstract: Most existing implementations of low-power electronic devices rely on the classical charge degree of freedom of electrons as the information carrier. Identifying the quantum characteristics of electrons as a new information carrier can provide a promising pathway to realize low-power electronics with functionality and performance far beyond traditional electronics. Quantum geometry—the intrinsic geometric structure of Bloch wavefunctions in momentum space—offers a compelling physical platform to address this challenge. In this talk, I will discuss our recent efforts of exploring quantum geometry in quantum materials, including its transport manifestation, non-volatile switching1, and finally the possibility of implementing a novel in-memory computing2.
References
[1] R. H. Wang et al, Nature Communications, 2025, 11298.
[2] R. H. Wang et al, Under review
Biography: Dr. Peng Song received his Bachelor degree in 2012 at Fudan University, and PhD degree in 2016 at National University of Singapore (NUS). From 2017 to 2021, he continued his postdoc research at NUS and then at Max Planck Institute of Microstructure Physics. His research in two-dimensional materials physics and electronic devices has led to several major breakthroughs in spin-orbit physics and publications in top scientific journals (Nature, Nature Materials etc). In May 2021, he was awarded the prestigious Nanyang Assistant Professorship and joined School of Electrical & Electronic Engineering, Nanyang Technological University (NTU) as an Assistant Professor. At NTU, he is interested in exploring novel device physics in low-dimensional materials and topological quantum materials, and their further integration into novel computing devices and architectures.
“Silicon devices for cryogenic computing” Qing-Tai Zhao - FZJ
Abstract: High-performance computing based on von Neumann architecture suffers from high power consumption at room temperature. Cryogenic computing, including von Neumann, neuromorphic and quantum systems, offers a way forward for highly energy-efficient big data processing. CMOS technology is central to this development, but it must operate at ultra-low power under cryogenic conditions. However, conventional CMOS, which is designed for room temperature, faces significant challenges at temperatures close to absolute zero. These include an increased subthreshold swing (SS) caused by band-tail effects, as well as an elevated threshold voltage resulting from bandgap widening and Fermi-level shifts. Addressing these issues is therefore critical. This presentation will discuss these challenges and the prospects for cryogenic CMOS. The use of a single transistor based on FDSOI FET for cryogenic memory will also be addressed.
Biography : Qing-Tai Zhao completed his PhD in physics at Peking University. He then joined the Institute of Microelectronics at Peking University as lecturer and associate professor, where he focused on the research of SOI materials and devices. In 1997, he was awarded a Humboldt Research Fellowship, which led him to Forschungszentrum Jülich in Germany, where he currently leads a research group specializing in nanoelectronic devices. His primary research interests include Si-Ge-Sn based high mobility devices and technology, FDSOI and nanowire devices for low power applications, as well as ferroelectric-based neuromorphic devices and cryogenic electronics for quantum computing. He has authored and co-authored around 300 peer-reviewed publications and holds over 40 patents.
Coffee Break
"Towards fab-compatible processing of 2D materials to neuromorphic computing devices" Burkay Uzlu - AMO
Abstract: Two-dimensional materials offer unique opportunities for next-generation applications due to their atomic thickness, electrostatic tunability, and compatibility with heterogeneous integration. In this talk, I will discuss progress toward fab-compatible wafer-scale processing of 2D materials and their integration into CMOS platforms. Key challenges such as variability, interface engineering, and scalable process modules will be highlighted. I will further present recent demonstrations of nanoscale memristive devices based on 2D materials and their integration onto silicon microchips, enabling low-voltage switching and potential applications in neuromorphic computing architectures.
Biography: Burkay Uzlu received his B.S. and M.S. degrees in Physics from Bilkent University, Turkey, and his Ph.D. in Electrical Engineering from RWTH Aachen University, Germany. He was a postdoctoral researcher at Northwestern University before joining AMO GmbH, where he currently works as a Research Associate. His research focuses on the development and scalable integration of two-dimensional (2D) materials for next-generation electronic and optoelectronic devices. His work includes wafer-scale fabrication, CMOS-compatible integration, and novel device concepts such as Dirac field-effect transistors (Dirac FETs) and memristive devices for emerging computing architectures.
"Embodied AI: When Intelligence Emerges from Hardware" Adrian Ionescu - EPFL
Abstract: Embodied Artificial Intelligence represents a paradigm shift in which intelligence emerges from the tight integration of sensing, actuation, computation, and learning within physical systems. Rather than treating AI as a purely algorithmic layer, embodied AI emphasizes the co-design of hardware, materials, and algorithms to enable adaptive, energy-efficient and context-aware behavior at the edge. This talk will introduce the core concepts of embodied AI and discuss the electronic technologies that enable it, including advanced sensors, bio-integrated and neuromorphic devices, in-memory and ferroelectric computing, and ultra-low-power edge architectures. Examples covering robotics, wearables and cyber-physical systems will illustrate how hardware–software co-design unlocks new capabilities beyond conventional AI platforms.
Biography: Adrian Ionescu is Full Professor of Nanoelectronics at EPFL and Director of the Nanoelectronic Devices Laboratory. His research focuses on advanced semiconductor devices, energy-efficient and neuromorphic electronics, bio-integrated sensors and hardware foundations for edge and embodied AI. He has authored more than 500 scientific publications and is the recipient of multiple ERC grants, IEEE awards, and international distinctions. Prof. Ionescu is actively involved in large-scale European and international initiatives at the intersection of AI, quantum electronics, nanoelectronics and health technologies, and is a founder or scientific advisor to several deep-tech startups. He currently serves in senior academic leadership roles at EPFL, where he contributes to strategic programs in engineering
"Nonlinear Multimode NEMS for Energy-Efficient Temporal Computing" Selim Hanay – INL
Abstract: As CMOS scaling approaches physical and energy-efficiency limits, alternative device concepts are being explored to enhance system-level computing performance. Nanoelectromechanical systems (NEMS) resonators provide intrinsic nonlinearity at ultra-low power, high quality factors, and compact footprints. In multimode NEMS devices, strong intra- and inter-modal coupling generates rich, high-dimensional dynamics, while long ring-down times enable short-term memory. These properties make NEMS attractive for physical reservoir computing and temporal signal processing. This talk presents experimental demonstrations of nonlinear multimode NEMS for time-series analysis and discusses their potential relevance to emerging heterogeneous and beyond-CMOS computing paradigms highlighted in IRDS roadmaps.
Biography: Selim Hanay is a Research Group Leader at INL – International Iberian Nanotechnology Laboratory. He received his B.Sc. in Microelectronics Engineering from Sabancı University and his Ph.D. in Physics from Caltech in 2011, where he developed NEMS-based single-molecule sensors. In 2013, he joined the faculty of Bilkent University, pioneering nonlinear NEMS and microwave resonator platforms for sensing and information processing. In 2025, he joined INL to advance NEMS-based computing architectures. He is the recipient of multiple national research awards and European Research Council (ERC) Starting and Proof-of-Concept grants.
Cocktail Dinner
