On September 18th, 2015, the 11th edition of the Sinano workshop devoted to “New Materials for Nanoelectronic” was held during ESSDERC-ESSCIRC’2015 in Graz, Austria, organized in collaboration with the EC project III-V-MOS (GA 619326).
Programm of the Workshops:
Presentations:
- Introduction, Enrico Sangiorgi, Director of the SINANO Institute, and Luca Selmi, III-V-MOS Project coordinator
- Integration of III-V devices on a Si platform, Nadine Collaert, IMEC
- TCAD device simulation frame for III-V MOS devices 1st part Fabian Bufler and “TCAD device simulation frame for III-V MOS devices” 2nd part Axel Erlebach , SYNOPSYS
- III-V Heterostructures and Transition Metal Dichalcogenides for Tunnel-FETsMarco Pala, IMEP-LAHC, Grenoble INP, CNRS
- Graphene and two-dimensional (2D) materials for NanoelectronicsGraphene and two-dimensional (2D) materials for Nanoelectronics, Vikram Passi, University of Siegen
- Investigating the high-k/InGaAs MOS System for Future Logic Applications, Scott Monaghan, Tyndall
- Demonstration and hands-on tutorial of atomic-scale simulation with ATK“, Troels Markussen and Umberto Pozzoni, QuantumWise
Minatec – CROMA